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Solved fig. 1 shows a two-level mux implementation of
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![Multiplexers in Digital Logic - GeeksforGeeks](https://i2.wp.com/media.geeksforgeeks.org/wp-content/uploads/4-35.png)
![8:1 mux : VLSI n EDA](https://2.bp.blogspot.com/-WrtBvWKZLrQ/V2v-PoHCxnI/AAAAAAAAAas/Sv4V7j4W2p4bvgGGrvYpXoSBpqphGtsHgCK4B/s1600/8x1%2Bmux%2Bstructure.png)
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![2x1 Mux Schematic](https://i2.wp.com/i.stack.imgur.com/YGkYh.png)